Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder

Authors:
Hafiz Md. Hasan Babu;Ahsan Raja Chowdhury
Affiliations:
University of Dhaka;University of Dhaka
Venue:
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Year:
2005

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Cited 1

A novel reversible TSG gate and its application for designing reversible carry look-ahead and other adder architectures

ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture

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Abstract

In this paper, we have proposed a design technique for the reversible circuit of Binary Coded Decimal (BCD) adder. The proposed circuit has the ability to add two4-bits binary variables and it transforms the addition into the appropriate BCD number with efficient error correcting modules where the operations are reversible. We also show that the proposed design technique generates the reversible BCD adder circuit with minimum number of gates as well as the minimum number of garbage outputs.