Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Design of Reversible Logic Circuits by Means of Control Gates
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Output Waveform Evaluation of Basic Pass Transistor Structure
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Evaluation of energy consumption in RC ladder circuits driven by a ramp input
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and comparison on full adder block in submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reversible computing: from mathematical group theory to electronical circuit experiment
Proceedings of the 2nd conference on Computing frontiers
Electronic Notes in Theoretical Computer Science (ENTCS)
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Reversible MOS or r-MOS is a logic family that inherently promises asymptotically-zero power consumption. We deduce a simple formula for calculating the power consumption. It rightly highlights the unfortunate influence of the threshold voltages of the MOS transistors.