Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
A modeling technique for CMOS gates
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power consumption in reversible logic addressed by a ramp voltage
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
| Hi-index | 0.00 |
Pass transistor logic is a promising alternative to conventional CMOS logic for low-power high-performance applications due to the decreased node capacitance and reduced transistor count it offers. However, the lack of supporting design automation tools has hindered the widespread application of pass transistors. In this paper, a simple and robust modeling technique for the timing analysis of the basic pass transistor structure is presented. The proposed methodology is based on the actual phenomena that govern the operation of the pass transistor and enables fast timing simulation of circuits that employ pass transistors as controlled switches without significant loss of accuracy, compared to SPICE simulation.