Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Performance analysis of low-power 1-Bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CMOS Logic Circuit Design
Digital Design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
A Novel Low Power Energy Recovery Full Adder Cell
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High speed gate level synchronous full adder designs
WSEAS Transactions on Circuits and Systems
Digital Design: Basic Concepts and Principles
Digital Design: Basic Concepts and Principles
A low power gate level full adder module
ASMCSS'09 Proceedings of the 3rd International Conference on Applied Mathematics, Simulation, Modelling, Circuits, Systems and Signals
A standard cell based synchronous dual-bit adder with embedded carry look-ahead
ECS'10/ECCTD'10/ECCOM'10/ECCS'10 Proceedings of the European conference of systems, and European conference of circuits technology and devices, and European conference of communications, and European conference on Computer science
A standard cell based synchronous dual-bit adder with embedded carry look-ahead
WSEAS Transactions on Circuits and Systems
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The binary full adder module is an important element present in processor data paths. The speed of computation that can be achieved in a processor data path is usually governed by the operating speed of the basic full adder. In fact, the full adder logic forms the basis of essential arithmetic operations like multiplication and division. Even subtraction in two's complement form is realized in a straightforward fashion using a linear cascade of full adders. Three novel gate level solutions, namely XNM, XNAIMC and XAC based full adder designs were presented in our earlier work. In this article, we present a succinct description of a further delay improved version. For a 32-bit adder/subtractor module (ASM) constructed using the ripple carry configuration and incorporating the proposed XOR, OR, AND and complex gates (XOAC) based full adder, corresponding speed improvement of 18.7%, 9.4% and 2.9% was achieved over the realizations utilizing the XNM, XNAIMC and XAC based full adders respectively. Comprehensive comparison with similar implementations encompassing only different gate level full adder designs further substantiate the speed efficiency of the proposed adder, all targeting the highest speed corner of the 65nm STMicroelectronics CMOS process.