Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Performance analysis of low-power 1-Bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Novel Low Power Energy Recovery Full Adder Cell
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High speed gate level synchronous full adder designs
WSEAS Transactions on Circuits and Systems
A delay improved gate level full adder design
ECC'09 Proceedings of the 3rd international conference on European computing conference
A standard cell based synchronous dual-bit adder with embedded carry look-ahead
ECS'10/ECCTD'10/ECCOM'10/ECCS'10 Proceedings of the European conference of systems, and European conference of circuits technology and devices, and European conference of communications, and European conference on Computer science
A standard cell based synchronous dual-bit adder with embedded carry look-ahead
WSEAS Transactions on Circuits and Systems
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A standard cell based gate level synchronous full adder design is presented in this paper. The main highlight of the article is that the proposed full adder realization is found to be better in terms of power-delay product (PDP), even in comparison with the full adder element that has been made available as part of two commercial standard cell libraries viz. the high-speed 130nm Faraday (UMC) bulk CMOS process technology and the low Vt but inherently power optimized 65nm STMicroelectronics bulk CMOS process. The fundamental ripple carry adder (RCA) topology is considered to demonstrate the power efficiency of our full adder module vis-à-vis many other recently proposed full adder module designs.