A standard cell based synchronous dual-bit adder with embedded carry look-ahead

Authors:
Padmanabhan Balasubramanian;Krishnamachar Prasad;Nikos E. Mastorakis
Affiliations:
WSEAS Research Department, Agiou Ioannou Theologou, Athens, Greece;Department of Electrical and Electronic Engineering, Auckland University of Technology, Auckland, New Zealand;Department of Computer Science, Military Institutions of University Education, Hellenic Naval Academy, Piraeus, Greece
Venue:
ECS'10/ECCTD'10/ECCOM'10/ECCS'10 Proceedings of the European conference of systems, and European conference of circuits technology and devices, and European conference of communications, and European conference on Computer science
Year:
2010

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Abstract

A novel synchronous dual-bit adder design, realized using the elements of commercial standard cell libraries, is presented in this article. The adder embeds two-bit carry look-ahead generator functionality and is realized using simple and compound gates of the standard cell library. The performance of the proposed dual-bit adder design is evaluated and compared vis-à-vis the conventional full adder (implemented using two half adder blocks) and the library's full adder element, when performing 32-bit addition on the basis of the fundamental carry propagate adder topology. Based on experimentations targeting the best case process corner of the high-speed 130nm UMC CMOS cell library and the highest speed corner of the inherently power optimized 65nm STMicroelectronics CMOS standard cell library, it has been found that the proposed adder module is effective in achieving significant performance gains even in comparison with the commercial library based adder whilst facilitating reduced energy-delay product.