Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Performance analysis of low-power 1-Bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
A CMOS VLSI Implementation of an Asynchronous ALU
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
A Novel Low Power Energy Recovery Full Adder Cell
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
All-optical arithmetic unit based on the hardlimiters
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Evolutionary techniques in circuit design and optimization
SMO'06 Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization
Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A delay improved gate level full adder design
ECC'09 Proceedings of the 3rd international conference on European computing conference
A low power gate level full adder module
ASMCSS'09 Proceedings of the 3rd International Conference on Applied Mathematics, Simulation, Modelling, Circuits, Systems and Signals
Adder designs using reversible logic gates
WSEAS Transactions on Circuits and Systems
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A novel synchronous dual-bit adder design, realized using the elements of commercial standard cell libraries is presented in this article. The adder embeds two-bit carry look-ahead generator functionality and is realized using simple and compound gates of the standard cell library. The performance of the proposed dual-bit adder design is evaluated and compared vis-à-vis the conventional full adder (implemented using two half adder blocks) and the library's full adder element, when performing 32-bit addition on the basis of the fundamental carry propagate adder topology. Based on experimentations targeting the best case process corner of the high-speed 130nm UMC CMOS cell library and the highest speed corner of the inherently power optimized 65nm STMicroelectronics CMOS standard cell library, it has been found that the proposed adder module is effective in achieving significant performance gains even in comparison with the commercial library based adder whilst facilitating reduced energy-delay product.