Adder designs using reversible logic gates

Authors:
P. K. Lala;J. P. Parkerson;P. Chakraborty
Affiliations:
Electrical Engineering Department, Texas A&M University-Texarkana, Texas;Computer Science and Computer Engineering Department, University of Arkansas, Fayetteville, Arkansas;Computer Science and Computer Engineering Department, University of Arkansas, Fayetteville, Arkansas
Venue:
WSEAS Transactions on Circuits and Systems
Year:
2010

Citing 7
Cited 2

Efficient Adder Circuits Based on a Conservative Reversible Logic Gate

ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
All-optical arithmetic unit based on the hardlimiters

EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Automatic design of optimal logic circuits based on ternary quantum-dot cellular automata

WSEAS Transactions on Circuits and Systems
High speed gate level synchronous full adder designs

WSEAS Transactions on Circuits and Systems
Irreversibility and heat generation in the computing process

IBM Journal of Research and Development
Logical reversibility of computation

IBM Journal of Research and Development
High-speed hardware efficient FIR compensation filter for Delta-Sigma modulator analog-to-digital converter in 0.13 µm CMOS technology

ICECS'05 Proceedings of the 4th WSEAS international conference on Electronics, control and signal processing

A standard cell based synchronous dual-bit adder with embedded carry look-ahead

WSEAS Transactions on Circuits and Systems
Ultra-area-efficient reversible multiplier

Microelectronics Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

A new reversible logic gate was proposed in Ref. [1]. This gate can be used to implement any classical Boolean logic function. This paper shows the application of the reversible gate in implementing ripple carry, carry skip and carry look-ahead adders. These adders are more efficient than adders implemented using Fredkin Gates.