Fault characterizations and design-for-testability technique for detecting $I_{DDQ}$ faults in CMOS/BiCMOS circuits

Authors:
Kaamran Raahemifar;Majid Ahmadi
Affiliations:
Electrical & Computer Engg. Dept., Ryerson Polytechnic University, Toronto, Ontario, Canada, M5B 2K3;Electrical Engineering Dept., University of Windsor, Windsor, Ontario, Canada, N9B 3P4
Venue:
Proceedings of the 38th annual Design Automation Conference
Year:
2001

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Abstract

This paper provides the results of a simulation-based fault characterization study of CMOS/BiCMOS logic families. We show that most of the shorts cause $I_{DDQ}$ faults, while open defects result in delay or stuck-open faults. We propose a design-for-testability technique for detecting short and bridging faults in CMOS/BiCMOS logic circuits. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated.