Parallel pattern fast fault simulation for three-state circuits and bidirectional I/O

Authors:
J. Th. van der Linden;M. H. Konijnenburg;A. J. van de Goor
Affiliations:
Department of Electrical Engineering, Delft University of Technology, Delft, The Netherlands;Department of Electrical Engineering, Delft University of Technology, Delft, The Netherlands;Department of Electrical Engineering, Delft University of Technology, Delft, The Netherlands
Venue:
ITC'94 Proceedings of the 1994 international conference on Test
Year:
1994

Citing 4
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Abstract

Industrial circuit designs commonly contain three-state elements, such as buses and drivers, transmission gates, and bidirectional I/O. A 5-valued fast fault simulation method and a 4-valued parallel pattern version that can handle these circuits are presented. Results demonstrate the effectiveness of the proposed methods in the presence of three-state elements, and show but a small performance degradation compared to 2- or 3-valued fault simulation.