A logic chip delay-test method based on system timing
IBM Journal of Research and Development
Petri Net based search directing heuristics for test generation
DAC '83 Proceedings of the 20th Design Automation Conference
SCIRTSS: A Search System for Sequential Circuit Test Sequences
IEEE Transactions on Computers
Efficiency of Random Compact Testing
IEEE Transactions on Computers
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks
IEEE Transactions on Computers
Procedures for increasing fault coverage for digital networks
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
Optimal logic synthesis and testability: two faces of the same coin
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Synthesis and optimization procedures for fully and easily testable sequential machines
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
An incomplete scan design approach to test generation for sequential machines
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
| Hi-index | 14.99 |
Two procedures are presented for generating fault detection test sequences for large sequential circuits. In the adaptive random procedure one can achieve a tradeoff between test generation time, length, and percent of circuit tested. An algorithmic path-sensitizing procedure is also presented. Both procedures employ a three-valued logic system. Some experimental results are given.