A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Analysis of Logic Circuits with Faults Using Input Signal Probabilities
IEEE Transactions on Computers
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks
IEEE Transactions on Computers
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
Defect Level as a Function of Fault Coverage
IEEE Transactions on Computers
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
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This paper uses a relation of fault coverage and defect level to determine the number of random patterns required to obtain a certain defect level. This technique has application to networks which use self-testing.