Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits
IEEE Transactions on Computers
Test generation for MOS circuits using D-algorithm
DAC '83 Proceedings of the 20th Design Automation Conference
A gate level model for CMOS combinational logic circuits with application to fault detection
DAC '84 Proceedings of the 21st Design Automation Conference
Minimum test patterns for residue networks
DAC '71 Proceedings of the 8th Design Automation Workshop
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The problem of single stuck-at, stuck-open, and stuck-on fault detection in cascode voltage switch (CVS) parity trees is considered. The results are also applied to parity and two-rail checkers. It is shown that, if the parity tree consists of only differential cascode voltage switch (DCVS) EX-OR gates, then the test set consists of at most five vectors (in some cases only four vectors are required) for detecting all detectable single stuck-at, stuck-open, and stuck-on faults, independent of the number of primary inputs and the number of inputs to any EX-OR gate in the tree. If, however, only a single-ended output is desired from the tree, then the final gate will be a single-ended cascode voltage switch (SCVS) EX-OR gate, for which the test set has only eight vectors. For a strongly self-checking (SSC) CVS parity checker, the size of a test set consisting of only codewords is nine, whereas for an SSC CVS two-rail checker the size of a test set consisting of only codewords is at most five.