CMOS VLSI challenges to test

Authors:
Kenneth D. Mandl
Affiliations:
Sperry Semiconductor Operations, Eagan, MN
Venue:
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Year:
1984

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Abstract

Challenges that CMOS VLSI technology present to the existing bipolar technology based test generation/grading tools and testability techniques are discussed in this paper. These challenges are in the areas of logic modeling, simulation capability and fault modeling.