A new switch-level test pattern generation algorithm based on single path over a graph representation

Authors:
C. Ferrer;J. Oliver;E. Valderrama
Affiliations:
Universitat Autònoma de Barcelona, 08193 Bellaterra (Barcelona), SPAIN;Universitat Autònoma de Barcelona, 08193 Bellaterra (Barcelona), SPAIN;Universitat Autònoma de Barcelona, 08193 Bellaterra (Barcelona), SPAIN
Venue:
EURO-DAC '90 Proceedings of the conference on European design automation
Year:
1990

Citing 2
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Transistor level test generation for MOS circuits

DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Graph Algorithms

Graph Algorithms

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Abstract

A new switch-level automatic test pattern generation algorithm for CMOS combinational network is presented. Such a generator can be applied to static and dynamic CMOS logics, and pseudo-NMOS ones. The fault model includes stuck-on and stuck-open transistor faults, although the algorithm can be easily generalized to open and short faults. The algorithm follows a PODEM-like strategy, and may be directly applied to a wide spread of CMOS logics. Test vector generation times have been notoriously improved, comparing with others switch-level algorithms.