DAC '82 Proceedings of the 19th Design Automation Conference
Automatic test-generation and test-verification of digital systems
DAC '74 Proceedings of the 11th Design Automation Workshop
Test generation for IDDQ testing and leakage fault detection in CMOS circuits
EURO-DAC '92 Proceedings of the conference on European design automation
Bridge fault simulation strategies for CMOS integrated circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Logic Testing of Bridging Faults in CMOS Integrated Circuits
IEEE Transactions on Computers
Detection of Defects Using Fault Model Oriented Test Sequences
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Transistor-level test generation for physical failures in CMOS circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Analog Integrated Circuits and Signal Processing - Special issue on selected papers from ECS '97
Test Generation for Current Testing (CMOS ICs)
IEEE Design & Test
Improving Defect Detection in Static-Voltage Testing
IEEE Design & Test
Serial transistor network modeling for bridging fault simulation
ATS '95 Proceedings of the 4th Asian Test Symposium
CCII+ Current Conveyor Based BIC Monitor for IDDQ Testing of Complex CMOS Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Comparison of Defect Detection Capabilities of Current-Based and Voltage-Based Test Methods
ETW '00 Proceedings of the IEEE European Test Workshop
Comparison of Defect Detection Capabilities of Current-Based and Voltage-Based Test Methods
ETW '00 Proceedings of the IEEE European Test Workshop
Testability-oriented channel routing
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Test Strategy Sensitivity to Defect Parameters
ITC '97 Proceedings of the 1997 IEEE International Test Conference
APPLICATION AND ANALYSIS OF IDDQ DIAGNOSTIC SOFTWARE
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
I-V Fast IDDQ Current Sensor for On-Line Mixed-Signal/Analog Test
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
A Comparison of Bridging Fault Simulation Methods
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A probabilistic fault model for analog faults
EURO-DAC '91 Proceedings of the conference on European design automation
Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks
Journal of Electronic Testing: Theory and Applications
Graphical IDDQ signatures reduce defect level and yield loss
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-line error detection and fast recover techniques for dependable embedded processors
On-line error detection and fast recover techniques for dependable embedded processors
Defect classes - an overdue paradigm for CMOS IC testing
ITC'94 Proceedings of the 1994 international conference on Test
Detecting bridging faults with stuck-at test sets
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits
Journal of Electronic Testing: Theory and Applications
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The stuck-at fault model, which is commonly used with fault simulation, does not adequately evaluate the effects of bridging faults (shorts between adjacent signal lines) in CMOS circuits. Tests for bridging faults can be performed on automatic test equipment, and the test vectors can be evaluated using logic simulation.