Test pattern generation for sequential MOS circuits by symbolic fault simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Built-in current testing
System-level routing of mixed-signal ASICs in WREN
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Design for testability view on placement and routing
EURO-DAC '92 Proceedings of the conference on European design automation
Testing for bridging faults (shorts) in CMOS circuits
DAC '83 Proceedings of the 20th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Modeling of integrated circuit defect sensitivities
IBM Journal of Research and Development
Design for manufacturability in submicron domain
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
| Hi-index | 0.00 |
The quality of IC testing can be improved by applying appropriate design strategies. In this paper, we present a testability-oriented routing methodology, which can be used to modify the IC layout so as to reduce the probability of test escape. A testability-oriented iterative channel routing tool based on this methodology has been developed. Example applications of this tool illustrating the methodology are also presented in the paper.