Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
E-PROOFS: a CMOS bridging fault simulator
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
IC Defects-Based Testability Analysis
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Fast and Accurate CMOS Bridging Fault Simulation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Testing CMOS Logic Gates for Realistic Shorts
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Testing for bridging faults (shorts) in CMOS circuits
DAC '83 Proceedings of the 20th Design Automation Conference
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The most recent bridging fault models, the voting and the biased voting model use the concept of relative transistor strength during fault simulation. A SPICE pre-simulation allows one to determine the relative strength of unit dimension transistors; the results stored in tables are then used during fault simulation. This concept is very efficient for single transistor and parallel transistor networks but suffers when serial transistor networks are considered. The relative strength of serial transistor networks implies the use of many tables (for 2, 3, 4, ... serial n and p transistors) slowing down the fault simulation procedure. This paper presents a new model for serial transistor networks which accelerates bridging fault simulation. This model allows one to easily define a single transistor equivalent to the serial network. In this way, any bridging fault involving any transistor network can be considered as a bridging fault involving single transistors. This model used with either the voting or the biased voting model decreases the number of required tables increasing the efficiency of the bridging fault simulation.