Testing CMOS Logic Gates for Realistic Shorts

VHDL fault simulation for defect-oriented test and diagnosis of digital ICs

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Logic Testing of Bridging Faults in CMOS Integrated Circuits

IEEE Transactions on Computers

Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems

Journal of Electronic Testing: Theory and Applications

Serial transistor network modeling for bridging fault simulation

ATS '95 Proceedings of the 4th Asian Test Symposium

A methodolgy for characterizing cell testability

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

13.1 A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

13.2 Sampling Techniques of Non-Equally Probable Faults in VLSI Systems

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium