Test generation for MOS circuits using D-algorithm
DAC '83 Proceedings of the 20th Design Automation Conference
COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
COSMOS: A compiled simulator for MOS circuits
25 years of DAC Papers on Twenty-five years of electronic design automation
A parallel pattern mixed-level fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
VHDL switch level fault simulation
EURO-DAC '94 Proceedings of the conference on European design automation
Fast incremental circuit analysis using extracted hierarchy
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits
Journal of Electronic Testing: Theory and Applications
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We describe SLS, a large capacity, high performance switch level simulator, developed to run on an IBM System/370 architecture, that uses a model which closely reflects the behavior of MOS circuits. This performance is the result of mixing a compiled model with the more traditional approach of event-driven simulation control, together with very efficient algorithms for evaluating the steady state response of the circuit. SLS is used for design verification/checking applications and for estimating fault coverage.