Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Generating Tests for Delay Faults in Nonscan Circuits
IEEE Design & Test
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
On Multiple Path Propagating Tests for Path Delay Faults
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Generation of Compact Delay Tests by Multiple-Path Activation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Functional test generation for non-scan sequential circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Robust testing for stuck-at faults
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
An efficient automatic test generation system for path delay faults in combinational circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Detection of Faults in Programmable Logic Arrays
IEEE Transactions on Computers
Energy models for delay testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a novel test generation technique for path delay faults, based on the growth (G) and disappearance (D) faults of programmable logic arrays (PLA). The circuit is modeled as a PLA that is prime and irredundant with respect to every output. Certain tests for G faults, generated by using known efficient methods are transformed into tests for path delay faults. Our algorithm generates tests for all robustly detectable path delay faults in the two-level circuit and its multilevel implementation synthesized using algebraic transformations. Experimental results confirm that the generated vectors, beside robustly covering all path delay faults, also cover most stuck faults in the algebraically factored multilevel circuit. We present some of the best known timings and robust path delay fault coverages for the scan/hold versions of several ISCAS89 circuits, for which the PLA description could be obtained.