Functional test generation for non-scan sequential circuits

Authors:
M. K. Srinivas;J. Jacob;V. D. Agrawal
Affiliations:
-;-;-
Venue:
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Year:
1995

Citing 5
Cited 1

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Multiple fault detection in two-level multi-output circuits

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Detection of Faults in Programmable Logic Arrays

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Functional test generation for path delay faults

ATS '95 Proceedings of the 4th Asian Test Symposium

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Abstract

The feasibility of generating high quality functional test vectors for sequential circuits using the Growth (G) and Disappearance (D) fault model has been demonstrated earlier. In this paper we provide a theoretical validation of the G and D fault model by proving the ability of this model to guarantee complete stuck fault coverage in combinational and sequential circuits synthesized employing algebraic transformations. We also provide experimental results on a wide range of synthesized FSMs. A comparison with a state-of-the-art gate level ATPG tool demonstrates the efficiency and limitation of the functional approach.