Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
At-speed delay testing of synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
SPADES: a simulator for path delay faults in sequential circuits
EURO-DAC '92 Proceedings of the conference on European design automation
The optimistic update theorem for path delay testing in sequential circuits
Journal of Electronic Testing: Theory and Applications
Generating Tests for Delay Faults in Nonscan Circuits
IEEE Design & Test
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Generation of Compact Delay Tests by Multiple-Path Activation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Quality Transition Fault Tests Suitable for Small Delay Defects
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
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Many test generation algorithms for path delay faults assume a special methodology for application of the test sequence. The two-vector test sequences are valid under the assumption that the combinational logic reaches a steady state following the first vector before the second vector is applied. While such vectors may be acceptable for combinational circuits, their use for testing a non-scan sequential circuit is virtually impossible where it is difficult to run the clock at a constant rate. Most multi-valued algebras for combinational circuits are rendered invalid when vectors are applied at the rated speed. We present a new multi-valued algebra and a test generation algorithm to derive tests for a uniform rated speed test application methodology. The main ideas in the paper include an algebra that derives three-vector test sequences combinational logic and (2) a value propagation rule for latches, resulting in more realistic fault coverages in sequential circuits when all vectors are applied at the rated speed. The test generator uses Boolean functions to reason about state transitions in sequential machines. These Boolean functions are stored and manipulated as Binary Decision Diagrams (BDDs). Experimental data on moderate size ISCAS89 benchmarks are included.