Deriving Logic Systems for Path Delay Test Generation
IEEE Transactions on Computers
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Sequential logic path delay test generation by symbolic analysis
ATS '95 Proceedings of the 4th Asian Test Symposium
Statistical path delay fault coverage estimation for synchronous sequential circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
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