Parallel pattern fault simulation of path delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
SPADES: a simulator for path delay faults in sequential circuits
EURO-DAC '92 Proceedings of the conference on European design automation
The optimistic update theorem for path delay testing in sequential circuits
Journal of Electronic Testing: Theory and Applications
An efficient path delay fault coverage estimator
DAC '94 Proceedings of the 31st annual Design Automation Conference
Statistical estimation of delay fault detectabilities and fault grading
Journal of Electronic Testing: Theory and Applications
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Probability and Statistics with Reliability, Queuing and Computer Science Applications
An Exact Non-Enumerative Fault Simulator for Path-Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
An efficient method for computing exact path delay fault coverage
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Statistical methods for delay fault coverage analysis
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Improving accuracy in path delay fault coverage estimation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Statistical path delay fault coverage estimation for synchronous sequential circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault coverage estimation by test vector sampling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
We present a technique to statistically estimatepath-delay fault coverage for synchronous sequential circuits.We perform fault-free simulation using a multivalue algebraand accumulate signal transition statistics, from which wecalculate controllabilities of all signals and sensitization probabilitiesfor all gates and flip-flops. We use a rated clock testing model where all time frames operate at the rated clock. We obtain path observabilities either by enumerating paths in the all-paths method, or by a nonenumerative method considering only the longest paths. The path-delay fault detectability is the product of observabilities of signals on paths from primary inputs (PIs) or pseudo-primary inputs (PPIs) to primary outputs (POs) or pseudo-primary outputs (PPOs), and the controllability on the corresponding PI or PPI. We use the optimistic update rule of Bose et al. for updating latches during logic simulation.When compared with exact fault simulation, the average absolute deviationin our statistical fault coverage estimation technique is 1.23% and the very worst absolute deviation was 6.59%. On average, our method accelerates delay fault coverage computation four times over an exact path delay fault simulator.