Maximum independent sets on transitive graphs and their applications in testing and CAD
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits
Journal of Electronic Testing: Theory and Applications
20.1 A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Exact Path Delay Grading with Fundamental BDD Operations
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Color Counting and its Application to Path Delay Fault Coverage
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Accurate Path Delay Fault Coverage is Feasible
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Implicit deductive fault simulation for complex delay fault models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implicit grading of multiple path delay faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Nonenumerative path-delay fault coverage estimation for combinational circuits estimates the fault coverage of a given test set without explicit enumeration of all paths in the circuit. In a recent nonenumerative method, it was proposed that a set C of lines be located in the circuit so that the set forms a cut and no lines in the set belong to the same path. Each line in the cut defines a subcircuit consisting of all paths that contain the line. Fault coverage may be obtained by working on all the subcircuits without double-counting path-delay faults. The main result of this paper is a polynomial time algorithm for finding a maximum cardinality set C. Besides its theoretical importance, our extensive experimental results on the ISCAS'85 benchmarks show that the larger the set C (and the number of subcircuits), the better the fault coverage estimation. More subcircuits may be generated only in a heuristic manner. It was proposed to consider two or more line-disjoint cuts Ci. We propose a technique where only one Ci must be a cut. This scheme is based on novel algorithms and results in more subcircuits than the previous one