An efficient path delay fault coverage estimator
DAC '94 Proceedings of the 31st annual Design Automation Conference
Maximum independent sets on transitive graphs and their applications in testing and CAD
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An Exact Non-Enumerative Fault Simulator for Path-Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
ATPD: An Automatic Test Pattern Generator for Path Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
An efficient method for computing exact path delay fault coverage
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Improving accuracy in path delay fault coverage estimation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Segment delay faults: a new fault model
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
NEST: a nonenumerative test generation method for path delay faults in combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improving a nonenumerative method to estimate path delay fault coverage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact Path Delay Grading with Fundamental BDD Operations
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Color Counting and its Application to Path Delay Fault Coverage
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
ATPG for Path Delay Faults without Path Enumeration
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Implicit deductive fault simulation for complex delay fault models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We examine the problem of determiningthe exact number of path delay faults that a given setof p pairs of patterns detects in a combinational circuitconsisting of l lines. Several fault coverage pessimisticheuristics and exact algorithms with worst case exponential behavior have been recently presented withtrade-offs between the quality of fault coverage andthe time performance. None of the existing approacheshas provably good performance. This paper presentsthe first polynomial time algorithms that calculate thepath delay fault coverage exactly. Experimental results on the ISCAS'85 benchmarks demonstrate theeffectiveness of the presented approaches.