Computational geometry: an introduction
Computational geometry: an introduction
Parallel pattern fault simulation of path delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An efficient non-enumerative method to estimate path delay fault coverage
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
The interdependence between delay-optimization of synthesized networks and testing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Data Structures and Algorithms
Data Structures and Algorithms
Random Pattern Testability of Delay Faults
IEEE Transactions on Computers
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Exact Path Delay Grading with Fundamental BDD Operations
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Color Counting and its Application to Path Delay Fault Coverage
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Accurate Path Delay Fault Coverage is Feasible
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Implicit deductive fault simulation for complex delay fault models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implicit grading of multiple path delay faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
We describe algorithms and data structures for accurate and efficient computation of path delay fault coverage. Our method uses an interval-based representation of consecutively numbered path delay faults. We describe a modified 2-3 tree data structure to store and manipulate these intervals to keep track of tested faults. Some results obtained using non-robust simulation of benchmark circuits suggest the viability of this approach.