Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
The optimistic update theorem for path delay testing in sequential circuits
Journal of Electronic Testing: Theory and Applications
An efficient path delay fault coverage estimator
DAC '94 Proceedings of the 31st annual Design Automation Conference
An efficient non-enumerative method to estimate path delay fault coverage
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Statistical methods for delay fault coverage analysis
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
IEEE Design & Test
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits
Journal of Electronic Testing: Theory and Applications
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We present the first technique to statistically estimate path delay-fault coverage for synchronous sequential circuits. We perform fault-free simulation using a multi-valued algebra and accumulate signal statistics, which we use to calculate path delay-fault coverage. The detectability of a path delay-fault is the product of observabilities from primary or pseudo-primary outputs to primary or pseudo-primary inputs, and the controllability on the corresponding primary or pseudo-primary inputs. We use the optimistic update rule of Bose et al. for updating latches during logic simulation. When compared with fault simulation results, the average error in statistical fault coverage using our technique is 2%. On average, the method accelerates fault coverage calculation two to five times over a delay-fault simulator, when all paths are considered.