IEEE Design & Test
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Hierarchical Delay Test Generation
Journal of Electronic Testing: Theory and Applications
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Statistical path delay fault coverage estimation for synchronous sequential circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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We have developed new statistical techniques for delay fault analysis. True value simulation is performed using a multi-value logic system describing signal states of two consecutive vectors. Signal statistics are used to estimate transition probabilities and observabilities. These allow us to estimate detection probabilities and the coverage for transition faults. For path delay faults, recognizing that the total number of possible paths can be exponential in circuit size, we devise an implicit random path sampling procedure to obtain a linear-time estimate of the coverage for all faults. We further derive a longest path theorem to estimate coverages with respect to longest paths through primary inputs and a selected set of fanout branches. Coverages are estimated for a minimal set of longest paths such that each signal lead is included in at least one target path whose propagation delay is no less than the delay of any path containing the lead. The fault coverage estimates closely agree with those obtained from delay fault simulation while giving a significant speedup.