LOT: logic optimization with testability—new transformations using recursive learning
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A novel combinational testability analysis by considering signal correlation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A STAFAN-like functional testability measure for register-level circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Statistical methods for delay fault coverage analysis
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
HISCOAP: a hierarchical testability analysis tool
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Statistical path delay fault coverage estimation for synchronous sequential circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Faster Fault Simulation Through Distributed Computing
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Exact probabilistic analysis of error detection for parity checkers
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A new framework for designing & analyzing BIST techniques: computation of exact aliasing probability
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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Statistical Fault Analysis, or Stafan, is proposed as an alternative to fault simulation of digital circuits. This methoddefines Controllabilities and observabilities of circuit nodes as probabilities estimated from signal statistics of fault-freesimulation. Special Procedures deal with these quantities at fanout and feedback nodes. The computed probabilities are usedto derive unbiased estimates of fault detection probabilities and overall fault coverage for the given set of input vectors.Among Stafan's advantages, fault coverage and the undetected fault data obtained for actual circuits are shown to agree withinfive percent of fault simulator results, yet CPU time and memory demands fall far short of those required in fault simulation.The Computational complexity added to a fault-free simulator by Stafan grows only linearly with the number of circuit nodes.