A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
IEEE Design & Test
Designing Self Test Programs for Embedded DSP Cores
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Self Test Program Design Technique for Embedded DSP Cores
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
STAFAN (statistical fault analysis) is a well known testability analysis program which predicts the fault coverage of a digital circuit under the stuck-at fault model, without actually performing fault simulation. STAFAN offers speed advantage over other testability analysis programs such as SCOAP; further, it explicitly predicts the fault coverage for a given test set, unlike other testability measures which are harder to interpret. STAFAN works on gate-level digital circuits composed of basic logic gates. In this work, we show how a STAFAN-like testability analysis program can be constructed for circuits built out of register-level modules. With the proliferation of high-level synthesis and testability-driven synthesis, it is becoming more and more important to have fast testability analysis tools which operate on register-level components such as adders, multipliers, multiplexers, busses, and so on. Our testability analysis algorithm, which we call F-STAFAN, fills this void. We have implemented F-STAFAN on a Sun/SPARC workstation and describe its performance on several register-level circuits.