The Transduction Method-Design of Logic Networks Based on Permissible Functions
IEEE Transactions on Computers
On the Complexity of Mod-2l Sum PLA's
IEEE Transactions on Computers
Test-set preserving logic transformations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Perturb and simplify: multi-level boolean network optimizer
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Random pattern testable logic synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Logic Synthesis and Optimization
Logic Synthesis and Optimization
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Can Redundancy Enhance Testability?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Automated Logic Synthesis of Random-Pattern-Testable Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
ATPG-based Transformations for Random-Pattern Testable Logic Synthesis
ATPG-based Transformations for Random-Pattern Testable Logic Synthesis
IEEE Design & Test
VERILAT: verification using logic augmentation and transformations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Gate-level synthesis for low-power using new transformations
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Sequential optimisation without state space exploration
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Pseudo-Kronecker Expressions for Symmetric Functions
IEEE Transactions on Computers
Design rewiring based on diagnosis techniques
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
BETSY: synthesizing circuits for a specified BIST environment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Test Point Insertion Algorithm for Mixed-Signal Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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Abstract: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates derived based on indirect implications by Recursive Learning have been introduced in the synthesis of multi-level circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology can not only realize lower area, but also achieves better testability compared to testability enhancement synthesis tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations can yield smaller circuits compared to state-of-the-art logic optimization tools like SIS and HANNIBAL.