Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
LOT: logic optimization with testability—new transformations using recursive learning
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An efficient equivalence checker for combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
A novel framework for logic verification in a synthesis environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Robust latch mapping for combinational equivalence checking
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Tight integration of combinational verification methods
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Applied Boolean Equivalence Verification and RTL Static Sign-Off
IEEE Design & Test
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This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is either not changed during the verification process, as in OBDD or implication-based methods, or the circuit is progressively reduced during verification. Whereas in our approach, we actually enlarge the circuits by adding gates during the verification process. Specifically introduced here is a new technique that transforms the reference circuit as well as the circuit to be verified, so that the similarity between the two is progressively enhanced. This requires addition of gates to the reference circuit and/or the circuit to be verified. In the process, we reduce the dissimilarity between the two circuits, which makes it easier to verify the circuits.