Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
Maximum independent sets on transitive graphs and their applications in testing and CAD
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Deriving Logic Systems for Path Delay Test Generation
IEEE Transactions on Computers
Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability
EDTC '96 Proceedings of the 1996 European conference on Design and Test
20.1 A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
| Hi-index | 0.01 |
Abstract: Some previously published results show that in a number of combinational circuits a significant portion of long paths is neither robustly nor non-robustly testable. However, not all of those untestable paths may be ignored in delay testing. Functional sensitizable paths are robust and non-robust untestable but, under some faulty conditions, may degrade the performance of the circuit. Even though the need for testing functional sensitizable paths was recognized in previous research, up till now, there was no strategy for generating tests for them. In this paper we present an algorithm for generating high quality tests for functional sensitizable paths based on including the timing information into the process of test derivation. Our experimental results prove that the quality of delay testing increases if additional test vectors for functional sensitizable path delay faults are included.