Theoretical Computer Science
STACS '03 Proceedings of the 20th Annual Symposium on Theoretical Aspects of Computer Science
Towards Bounded Model Checking for the Universal Fragment of TCTL
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Data-Structures for the Verification of Timed Automata
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
Checking reachability properties for timed automata via SAT
Fundamenta Informaticae - Concurrency specification and programming
Improvements in SAT-based Reachability Analysis for Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)
Bounded Model Checking for the Existential Fragment of TCTL_{-G} and Diagonal Timed Automata
Fundamenta Informaticae
Verifying Security Protocols Modelled by Networks of Automata
Fundamenta Informaticae - Special Issue on Concurrency Specification and Programming (CS&P)
SAT-Based Reachability Checking for Timed Automata with Discrete Data
Fundamenta Informaticae - Special Issue on Concurrency Specification and Programming (CS&P)
Model Checking and Artificial Intelligence
SAT-Based Verification of Security Protocols Via Translation to Networks of Automata
Model Checking and Artificial Intelligence
VerICS 2007 - a Model Checker for Knowledge and Real-Time
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
SAT-based (parametric) reachability for a class of distributed time Petri nets
Transactions on Petri nets and other models of concurrency IV
Parametric model checking with verICS
Transactions on Petri nets and other models of concurrency IV
Exact incremental analysis of timed automata with an SMT-solver
FORMATS'11 Proceedings of the 9th international conference on Formal modeling and analysis of timed systems
SAT based bounded model checking with partial order semantics for timed automata
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
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This paper deals with the problemof checking reachability for timed automata with diagonal constraints. Such automata are needed in many applications e.g. to model scheduling problems. We introduce a new discretization for timed automata which enables SAT based reachability analysis for timed automata for which comparisons between two clocks are allowed. In our earlier papers SAT based reachability analysis was restricted to the so called diagonal-free timed automata, where only comparisons between clocks and constants are allowed.