A Unified Approach for Combining Different Formalisms for Hardware Verification
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Symbolic model checking for a discrete clocked temporal logic with intervals
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
The Verus Tool: A Quantitative Approach to the Formal Verification of Real-Time Systems
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Some Progress in the Symbolic Verification of Timed Automata
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Data-Structures for the Verification of Timed Automata
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Do You Trust Your Model Checker?
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Modleing and Checking Networks of Communicating Real-Time Process
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Symbolic Verification and Analysis of Discrete Timed Systems
Formal Methods in System Design
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In this paper we show that multi-terminal BDDs (MTBDDs) are well suited to represent and manipulate interval based timed transition systems. For many timed verification tasks efficient MTBDD-based algorithms are presented. This comprises the composition of timed structures based on symbolic techniques, heuristics for state variable minimization, and a symbolic model checking algorithm. Experimental results show that in many cases our approach outperforms standard unit-delay approaches and corresponding timed automata models.