Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
Bounded Model Checking for Timed Systems
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
Proceedings of the 31st ACM SIGPLAN-SIGACT symposium on Principles of programming languages
An interpolating theorem prover
Theoretical Computer Science - Tools and algorithms for the construction and analysis of systems (TACAS 2004)
Towards a Hybrid Dynamic Logic for Hybrid Dynamic Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Interpolant-based transition relation approximation
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Stochastic Games for Verification of Probabilistic Timed Automata
FORMATS '09 Proceedings of the 7th International Conference on Formal Modeling and Analysis of Timed Systems
SAT-based Verification for Timed Component Connectors
Electronic Notes in Theoretical Computer Science (ENTCS)
A framework for verification of software with time and probabilities
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
Differential dynamic logics: automated theorem proving for hybrid systems
Differential dynamic logics: automated theorem proving for hybrid systems
Compositional construction of real-time dataflow networks
COORDINATION'10 Proceedings of the 12th international conference on Coordination Models and Languages
SAT-based verification for timed component connectors
Science of Computer Programming
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In this paper, we present an abstraction refinement approach for model checking safety properties of real-time systems using SAT-solving. We present a faithful embedding of bounded model checking for systems of timed automata into propositional logic with linear arithmetic and prove correctness. With this logical representation, we achieve a linear-size representation of parallel composition and introduce a quick abstraction technique that works uniformly for clocks, events, and states. When necessary, abstractions are refined by analysing spurious counterexamples using a promising extension of counterexample-guided abstraction refinement with syntactic information about Craig interpolants. To support generalisations, our overall approach identifies the algebraic and logical principles required for logic-based abstraction refinement.