Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
A technique of state space search based on unfolding
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
LP Deadlock Checking Using Partial Order Dependencies
CONCUR '00 Proceedings of the 11th International Conference on Concurrency Theory
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets
Proceedings of the 16th International Conference on Application and Theory of Petri Nets
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CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Deadlock Checking Using Net Unfoldings
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Slack Elasticity in Concurrent Computing
MPC '98 Proceedings of the Mathematics of Program Construction
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
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ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Slack Matching Quasi Delay-Insensitive Circuits
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
A Theory of Asynchronous Control Networks
IEEE Transactions on Computers
Automated Verification of Asynchronous Circuits Using Circuit Petri Nets
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
Performance estimation and slack matching for pipelined asynchronous architectures with choice
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Teak: A Token-Flow Implementation for the Balsa Language
ACSD '09 Proceedings of the 2009 Ninth International Conference on Application of Concurrency to System Design
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Symbolic model checking for sequential circuit verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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It is important to verify the absence of deadlocks in asynchronous circuits. Much previous work relies on a reachability analysis of the circuits' states, with the use of binary decision diagrams (BDDs) or Petri nets to model the behaviors of circuits. This paper presents an alternative approach focusing on the structural properties of well-formed asynchronous circuits that will never suffer deadlocks. A class of data-driven asynchronous pipelines is targeted in this paper, which can be viewed as a network of basic components connected by handshake channels. The sufficient and necessary conditions for a component network consisting of Steer, Merge, Fork and Join are given. The slack elasticity of the channels is analyzed in order to introduce pipelining. As an application, a deadlock checking method is implemented in a syntax-directed asynchronous design tool - Teak. The proposed method shows a great runtime advantage when compared against previous Petri net based verification tools.