Structure-based deadlock checking of asynchronous circuits
Journal of Computer Science and Technology - Special issue on Natural Language Processing
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This paper describes a new target component set and synthesis scheme for the Balsaasynchronous hardware description language.This new scheme removes the reliance on precise handshake interleavingand enclosure by separating out control `go' and `done' signalling into separate channels ratherthan using different phases of the asynchronous handshake.This leads to circuits in which optimisationand control overhead mitigation can be carried out by merging/separating control and data channels and byintroducing handshake-decoupling latches.This work aims to make Balsa descriptions implementable inthe more widely used and understood higher performance token-based asynchronous circuit styles.