Verification method of dataflow algorithms in high-level synthesis
Journal of Systems and Software
Syntax-driven Behavior Partitioning for Model-checking of Esterel Programs
Electronic Notes in Theoretical Computer Science (ENTCS)
An enhanced flow analysis technique for detecting unreachability faults in concurrent systems
Information Sciences: an International Journal
Structure-based deadlock checking of asynchronous circuits
Journal of Computer Science and Technology - Special issue on Natural Language Processing
Predicting protein folding kinetics via temporal logic model checking
WABI'07 Proceedings of the 7th international conference on Algorithms in Bioinformatics
Multi-Core BDD Operations for Symbolic Reachability
Electronic Notes in Theoretical Computer Science (ENTCS)
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The temporal logic model checking algorithm of Clarke, Emerson, and Sistla (1986) is modified to represent state graphs using binary decision diagrams (BDD's) and partitioned transition relations. Because this representation captures some of the regularity in the state space of circuits with data path logic, we are able to verify circuits with an extremely large number of states. We demonstrate this new technique on a synchronous pipelined design with approximately 5×10120 states. Our model checking algorithm handles full CTL with fairness constraints. Consequently, we are able to express a number of important liveness and fairness properties, which would otherwise not be expressible in CTL. We give empirical results on the performance of the algorithm applied to both synchronous and asynchronous circuits with data path logic