On process-algebraic verification of asynchronous circuits

Authors:
X. Wang;M. Kwiatkowska
Affiliations:
University of Birmingham;University of Birmingham
Venue:
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Year:
2006

Citing 0
Cited 4

Compositional State Space Reduction Using Untangled Actions

Electronic Notes in Theoretical Computer Science (ENTCS)
On Process-algebraic Verification of Asynchronous Circuits

Fundamenta Informaticae - Half a Century of Inspirational Research: Honoring the Scientific Influence of Antoni Mazurkiewicz
On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP

Science of Computer Programming
On Process-algebraic Verification of Asynchronous Circuits

Fundamenta Informaticae - Half a Century of Inspirational Research: Honoring the Scientific Influence of Antoni Mazurkiewicz

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper develops a theoretical basis for using process algebra and associated model checking tools to verify asynchronous circuits. We extend existing verification theory for asynchronous circuits, and integrate it into the framework of standard process algebra theory. Our theory permits analysis of safeness (i.e. choke) and progress (i.e. illegal stop, divergence and relative starvation) conditions. We show how the model can be translated into CSP, and how the satisfaction of safeness and progress requirements can be reduced to refinement checks in CSP.