Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
What are the limits of model checking methods for the verification of real life protocols?
Proceedings of the international workshop on Automatic verification methods for finite state systems
Compilation and verification of LOTOS specifications
Proceedings of the IFIP WG6.1 Tenth International Symposium on Protocol Specification, Testing and Verification X
An Optimizing Compiler for Efficient Model Checking
FORTE XII / PSTV XIX '99 Proceedings of the IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XII) and Protocol Specification, Testing and Verification (PSTV XIX)
State space reduction based on live variables analysis
Science of Computer Programming - Special issue on static analysis (SAS'99)
Static Analysis for State-Space Reductions Preserving Temporal Logics
Formal Methods in System Design
On-the-Fly Data Flow Analysis Based on Verification Technology
Electronic Notes in Theoretical Computer Science (ENTCS)
Reflections on the Future of Concurrency Theory in General and Process Calculi in Particular
Electronic Notes in Theoretical Computer Science (ENTCS)
State Space Reduction of Linear Processes Using Control Flow Reconstruction
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
CADP 2006: a toolbox for the construction and analysis of distributed processes
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Translating FSP into LOTOS and networks of automata
IFM'07 Proceedings of the 6th international conference on Integrated formal methods
C.OPEN and ANNOTATOR: tools for on-the-fly model checking C programs
Proceedings of the 14th international SPIN conference on Model checking software
Ten years of performance evaluation for concurrent systems using CADP
ISoLA'10 Proceedings of the 4th international conference on Leveraging applications of formal methods, verification, and validation - Volume Part II
CADP 2010: a toolbox for the construction and analysis of distributed processes
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Model checking and co-simulation of a dynamic task dispatcher circuit using CADP
FMICS'11 Proceedings of the 16th international conference on Formal methods for industrial critical systems
A model-extraction approach to verifying concurrent C programs with CADP
Science of Computer Programming
Formal analysis of a hardware dynamic task dispatcher with CADP
Science of Computer Programming
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Data-flow analysis to identify "dead" variables and reset them to an "undefined" value is an effective technique for fighting state explosion in the enumerative verification of concurrent systems. Although this technique is well-adapted to imperative languages, it is not directly applicable to value-passing process algebras, in which variables cannot be reset explicitly due to the single-assignment constraints of the functional programming style. This paper addresses this problem by performing data-flow analysis on an intermediate model (Petri nets extended with state variables) into which process algebra specifications can be translated automatically. It also addresses important issues such as avoiding the introduction of useless reset operations and handling shared read-only variables that child processes inherit from their parents.