Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Compositional Modeling in Metropolis
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
A behavioral type system and its application in Ptolemy II
Formal Aspects of Computing
ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality
MASCOTS '05 Proceedings of the 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
Models of Computation for Networks on Chip
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Cross-layer power management in wireless networks and consequences on system-level architecture
Signal Processing - Special section: Advances in signal processing-assisted cross-layer designs
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Multi-granularity noc simulation framework for early phase exploration of SDR hardware platforms
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Microprocessors & Microsystems
A Case Study of Simulation and Performance Evaluationof a SDR Baseband Architecture
Journal of Signal Processing Systems
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Software Defined Radio (SDR) terminals are crucial to enable seamless and transparent inter-working between fourth generation wireless access systems or communication modes. On the longer term, SDRs will be extended to become Cognitive Radios enabling efficient spectrum usage. Future communication modes will have heavy hardware resource requirements and switching between them will introduce dynamism in respect with timing and size of resource requests. In this paper, we propose a modeling framework that enables the simulation of such complex, dynamic hardware/software SDR designs. Thus, we can do an exploration, which can pinpoint the coarse grain platform component requirements for future SDR applications in a very early design phase. Our solution differs from existing ones by combining multiple simulation granularities in a way that is specialized for SDR simulation. Finally, we demonstrate the effectiveness of our approach with a case study for dimensioning the on-chip interconnect of a prospective SDR platform.