Interprocessor Traffic Scheduling Algorithm for Multiple-Processor Networks
IEEE Transactions on Computers
Deflection routing in certain regular networks
Deflection routing in certain regular networks
The turn model for adaptive routing
25 years of the international symposia on Computer architecture (selected papers)
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Partitioning and Scheduling Parallel Programs for Multiprocessors
Partitioning and Scheduling Parallel Programs for Multiprocessors
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
StepNP: A System-Level Exploration Platform for Network Processors
IEEE Design & Test
IEEE Transactions on Parallel and Distributed Systems
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Packetization and routing analysis of on-chip multiprocessor networks
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Software tools for modeling and simulation of on-chip communication architectures
Software tools for modeling and simulation of on-chip communication architectures
ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality
MASCOTS '05 Proceedings of the 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Current uni-processor centric modelling methodology does not address the new design challenges introduced by MPSoCs, thus, calling for efficient simulation frameworks capable of capturing the interplay between the application, the architecture, and the network. Addressing these new challenges requires a framework that assists the designer at different abstraction levels of system design. This paper concentrates on developing a framework for unified simulation environment for NoCs (fuse-N), which simplifies the design space exploration for NoCs by offering a comprehensive simulation support. The framework synthesises the network infrastructure and the communication model and optimises application mapping for design constraints. The paper also proposes an efficient traffic aware scheduling algorithm that optimises the mapping problem by dynamically determining the latency by considering the communication and execution costs. The framework follows a top-down paradigm, where each design space component is implemented as modular components and all design constraints are captured and evaluated coherently. The proposed framework is a hardware-software co-design implementation using SystemC 2.1 and C++. Simulation results show the various design space explorations that can be performed by our framework.