A unified design space simulation environment for network-on-chip: fuse-N
International Journal of High Performance Systems Architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In multiprocessor based systems-on-chips (SoCs), optimizing the communication architecture is often as important as, if not more than, optimizing the computation architecture. Designers need to make important choices related to the on-chip communication architectures, i.e. Network-on-Chips (NoCs). These choices are often not self-evident. Designers need to understand the interplay between the application, the Processor Element (PE) architecture and the NoC to make the right decisions. At the same time, there is a tremendous pressure on designers to accelerate the “time-to-market” of their design without sacrificing the design quality. Achieving this requires a set of design automation tools which can model, simulate and verify the components of the system design before the silicon is available. Thus, a major challenge in designing the NoC is to build an efficient and accurate model for simulation and performance evaluation. The contributions of this dissertation are twofold. First, a new methodology based on modular design and object-oriented modeling techniques is proposed. This methodology is based on an object-oriented class hierarchy for the NoC and a dedicated NoC module library organized according to this hierarchical structure. Second, a retargetable simulation framework is developed where SoC designs can be constructed easily and evaluated efficiently and faithfully. The modeling and simulation platform is based on a formal concurrency model, the Operation State Machine (OSM). The NoC models are constructed faithfully by explicitly modeling both the operation concurrency and the microarchitecture concurrency. Coupled with existing PE models, this framework is capable of synthesizing a multiprocessor cycle-accurate SoC simulator from a system-level description. The case studies include a router-based packet-switching on-chip communication network and an industry-standard on-chip bus architecture. Experiment results show that this framework can significantly reduce the design turnaround time and improve design reuse in the early stages of SoC design.