Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Graph Theory With Applications
Graph Theory With Applications
Efficient circuit partitioning algorithms for parallel logic simulation
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
The maximum concurrent flow problem
Journal of the ACM (JACM)
A network-topology independent task allocation strategy for parallel computers
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Heuristic Technique for Processor and Link Assignment in Multicomputers
IEEE Transactions on Computers
Traffic Routing for Multicomputer Networks with Virtual Cut-Through Capability
IEEE Transactions on Computers
Supporting sets of arbitrary connections on iWarp through communication context switches
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
IEEE Transactions on Computers
Hypertool: A Programming Aid for Message-Passing Systems
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
A Generalized Scheme for Mapping Parallel Algorithms
IEEE Transactions on Parallel and Distributed Systems
A Framework for Mapping Periodic Real-Time Applications on Multicomputers
IEEE Transactions on Parallel and Distributed Systems
Using graph theory to reduce communication overhead in parallel systems
Journal of Computing Sciences in Colleges
HPC-Colony: services and interfaces for very large systems
ACM SIGOPS Operating Systems Review
Topology-aware task mapping for reducing communication contention on large parallel machines
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A unified design space simulation environment for network-on-chip: fuse-N
International Journal of High Performance Systems Architecture
| Hi-index | 14.99 |
Recent research on parallel systems has shown that the most difficult problem for system designers and users is interprocessor connection and communication. A methodology for the automated design and implementation of interprocessor communication for certain multiple-processor systems has been developed and is presented in this paper. For many application- specific and mission-oriented systems, the interprocessor communication is deterministic and can be specified at system inception. This specification can then be automatically mapped or complied onto a physical multiple-processor system using a network traffic scheduler. An algorithm for such a scheduler, which is capable of obtaining optimal network traffic patterns, has been developed. It is shown that the order of complexity of network scheduler components is polynomial, rather than expopential as in classical solutions.