Industrial experience using rule-driven retargetable code generation for multimedia applications
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Proceedings of the conference on Design, automation and test in Europe
StepNP: A System-Level Exploration Platform for Network Processors
IEEE Design & Test
Instruction Scheduler Generation for Retargetable Compilation
IEEE Design & Test
FlexCC2: An Optimizing Retargetable C Compiler for DSP Processors
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
System-on-chip beyond the nanometer wall
Proceedings of the 40th annual Design Automation Conference
Network Processing Challenges and an Experimental NPU Platform
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Non-transparent debugging for software-pipelined loops
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
A fully-non-transparent approach to the code location problem
SCOPES '08 Proceedings of the 11th international workshop on Software & compilers for embedded systems
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
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Complex systemson chips (SoCs) use embedded processors to deliver a combination of flexibility and competitive cost, power, and performance. Embedded processors that use reduced-instruction-set computers (RISCs) are the most common, but they do not offer any particular competitive advantage, because all companies have access to the same general-purpose embedded processor. Traditionally, special-purpose hardware (digital or analog) is necessary to gain a competitive advantage in performance,cost, or power. An increasingly popular alternative is the application-specific instruction-set processor (ASIP), which combines the flexibility of general-purpose processors with an optimized application-or domain-specific architecture thatcan significantly improve performance. Using a more effective architecture helps reduce voltage and save power.