Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Computer Systems (TOCS)
Proceedings of the conference on Design, automation and test in Europe
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
FlexWare: A Retargetable Embedded-Software Development Environment
IEEE Design & Test
Developing Architectural Platforms: A Disciplined Approach
IEEE Design & Test
StepNP: A System-Level Exploration Platform for Network Processors
IEEE Design & Test
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
NPSE: A High Performance Network Packet Search Engine
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
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The fast-changing communications market requires high-performance yet flexible network-processing platforms. StepNP驴 is an exploratory network processor simulation environment for exploring router applications, multiprocessor network-processing architectures, and SoC tools. Supporting model interaction, instrumentation, and analysis, the platform lets R&D teams easily add new processors, coprocessors, and interconnects.