Automating the Design of SOCs Using Cores
IEEE Design & Test
Proceedings of the 43rd annual Design Automation Conference
Support for partial run-time reconfiguration of platform FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs
Journal of Systems Architecture: the EUROMICRO Journal
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
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In this paper, an Autonomous Fault Tolerant System that implements a communication gateway between a CAN bus and asynchronous communication interface is presented. This gateway has been implemented using a Triple Modular Redundancy architecture at IP core level. The system can respond to an error detected by a voter in a Triple Modular Redundancy architecture reconfiguring the module that fails using pre-defined bitstreams. The whole system has been implemented in a Virtex-4 FPGA and the reconfiguration system is based on a hard PowerPC microprocessor.